1 data sheet acquired from harris semiconductor schs224 features ? typical propagation delay - 6ns at v cc = 5v, t a = 25 o c, c l = 50pf ? exceeds 2kv esd protection mil-std-883, method 3015 ? scr-latchup-resistant cmos process and circuit design ? speed of bipolar fast?/as/s with signi?cantly reduced power consumption ? balanced propagation delays ? ac types feature 1.5v to 5.5v operation and balanced noise immunity at 30% of the supply ? 24ma output drive current - fanout to 15 fast? ics - drives 50 w transmission lines description the cd74ac02 and cd74act02 are quad 2-input nor gates that utilize the harris advanced cmos logic technology. pinout cd74ac02, cd74act02 (pdip, soic) top view functional diagram ordering information part number temp. range ( o c) package pkg. no. CD74AC02E -55 to 125 14 ld pdip e14.3 cd74act02e -55 to 125 14 ld pdip e14.3 cd74ac02m -55 to 125 14 ld soic m14.15 cd74act02m -55 to 125 14 ld soic m14.15 notes: 12. when ordering, use the entire part number. add the suffix 96 to obtain the variant in the tape and reel. 13. wafer and die for this part number is available which meets all elec- trical specifications. please contact your local sales office or harris customer service for ordering information. 1y 1a 1b 2y 2a 2b gnd v cc 4y 4b 4a 3y 3b 3a 1 2 3 4 5 6 7 14 13 12 11 10 9 8 truth table inputs outputs aby llh hll lhl hhl 1a 1b 2a 2b 3a 3b 4a 4b 2 3 5 6 8 9 11 12 1 4 10 13 1y 2y 3y 4y gnd = 7 v cc = 14 september 1998 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. fast? is a trademark of fairchild semiconductor. copyright ? harris corporation 1998 cd74ac02, cd74act02 quad 2-input nor gate file number 1978.1 [ /title (cd74 ac02, cd74 act02 ) /sub- ject (quad 2-input nor gate) /autho r () /key- words (har- ris semi- con- ductor, advan ced cmos , harris semi- con- ductor, advan ced ttl) /cre- ator ()
2 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 6v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 50ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 50ma dc v cc or ground current, i cc or i gnd (note 3) . . . . . . . . . 100ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc (note 4) ac types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5v to 5.5v act types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall slew rate, dt/dv ac types, 1.5v to 3v . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (max) ac types, 3.6v to 5.5v . . . . . . . . . . . . . . . . . . . . . . . . 20ns (max) act types, 4.5v to 5.5v. . . . . . . . . . . . . . . . . . . . . . . 10ns (max) thermal resistance (typical, note 5) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 maximum junction temperature (plastic package) . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. notes: 14. for up to 4 outputs per device, add 25ma for each additional output. 15. unless otherwise specified, all voltages are referenced to ground. 16. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min max min max min max ac types high level input voltage v ih - - 1.5 1.2 - 1.2 - 1.2 - v 3 2.1 - 2.1 - 2.1 - v 5.5 3.85 - 3.85 - 3.85 - v low level input voltage v il - - 1.5 - 0.3 - 0.3 - 0.3 v 3 - 0.9 - 0.9 - 0.9 v 5.5 - 1.65 - 1.65 - 1.65 v high level output voltage v oh v ih or v il -0.05 1.5 1.4 - 1.4 - 1.4 - v -0.05 3 2.9 - 2.9 - 2.9 - v -0.05 4.5 4.4 - 4.4 - 4.4 - v -4 3 2.58 - 2.48 - 2.4 - v -24 4.5 3.94 - 3.8 - 3.7 - v -75 (note 6, 7) 5.5 - - 3.85 - - - v -50 (note 6, 7) 5.5---- 3.85 - v cd74ac02, cd74act02
3 low level output voltage v ol v ih or v il 0.05 1.5 - 0.1 - 0.1 - 0.1 v 0.05 3 - 0.1 - 0.1 - 0.1 v 0.05 4.5 - 0.1 - 0.1 - 0.1 v 12 3 - 0.36 - 0.44 - 0.5 v 24 4.5 - 0.36 - 0.44 - 0.5 v 75 (note 6, 7) 5.5 - - - 1.65 - - v 50 (note 6, 7) 5.5----- 1.65 v input leakage current i i v cc or gnd - 5.5 - 0.1 - 1- 1 m a quiescent supply current ssi i cc v cc or gnd 0 5.5 - 4 - 40 - 80 m a act types high level input voltage v ih - - 4.5 to 5.5 2-2-2- v low level input voltage v il - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 v high level output voltage v oh v ih or v il -0.05 4.5 4.4 - 4.4 - 4.4 - v -24 4.5 3.94 - 3.8 - 3.7 - v -75 (note 6, 7) 5.5 - - 3.85 - - - v -50 (note 6, 7) 5.5---- 3.85 - v low level output voltage v ol v ih or v il 0.05 4.5 - 0.1 - 0.1 - 0.1 v 24 4.5 - 0.36 - 0.44 - 0.5 v 75 (note 6, 7) 5.5 - - - 1.65 - - v 50 (note 6, 7) 5.5----- 1.65 v input leakage current i i v cc or gnd - 5.5 - 0.1 - 1- 1 m a quiescent supply current ssi i cc v cc or gnd 0 5.5 - 4 - 40 - 80 m a additional supply current per input pin ttl inputs high 1 unit load d i cc v cc -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 ma notes: 17. test one output at a time for a 1-second maximum duration. measurement is made by forcing current and measuring voltage to minimize power dissipation. 18. test verifies a minimum 50 w transmission-line-drive capability at 85 o c, 75 w at 125 o c. act input load table input unit load all 0.32 note: unit load is d i cc limit specified in dc electrical specifications table, e.g., 2.4ma max at 25 o c. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min max min max min max cd74ac02, cd74act02
4 switching speci?cations input t r , t f = 3ns, c l = 50pf (worst case) parameter symbol v cc (v) -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max ac types propagation delay, input to output t plh , t phl 1.5 - - 131 - - 144 ns 3.3 (note 9) 4.1 - 14.6 4 - 16.1 ns 5 (note 10) 3 - 10.4 2.9 - 11.5 ns input capacitance c i - - -10- -10pf power dissipation capacitance c pd (note 11) - - 55 - - 55 - pf act types propagation delay, input to output t plh , t phl 5 (note 10) 3.1 - 11.1 3.1 - 12.2 ns input capacitance c i - - -10- -10pf power dissipation capacitance c pd (note 11) - - 55 - - 55 - pf notes: 19. limits tested at 100%. 20. 3.3v min at 3.6v, max at 3v. 21. 5v min at 5.5v, max at 4.5v. 22. c pd is used to determine the dynamic power consumption per gate. ac: p d = v cc 2 f i (c pd + c l ) act: p d = v cc 2 f i (c pd + c l ) + v cc d i cc where f i = input frequency, c l = output load capacitance, v cc = supply voltage. dut output r l (note) output load 500 w c l 50pf note: for ac series only: when v cc = 1.5v, r l = 1k w. figure 2. propagation delay times cd74ac cd74act input level v cc 3v input switching voltage, v s 0.5 v cc 1.5v output switching voltage, v s 0.5 v cc 0.5 v cc figure 3. propagation delay times t r = 3ns t f = 3ns 90% v s 10% gnd input t phl t plh v s level v i v o cd74ac02, cd74act02
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